Intel just unveiled the new Foveros 3D stacking chip, which is an industry-first implementation of stacked processing components inside a chip.

Stacked memory is already available on smartphones. Now, Intel is doing something similar with the CPU, allowing its designers to essentially drop in extra processing power on top of an already assembled chip die. So your on-die memory, power regulation, graphics, and AI processing can all constitute separate chiplets, some of which can be stacked atop one another.

The benefits of greater computational density and flexibility are obvious, but this modular approach also helps Intel to get around one of its biggest challenges: building full chips at 10nm scale.

On the way to Foveros, Intel suggests it will do something it calls 2D stacking, which is a separation of the various processor components into smaller chiplets, each of which can be manufactured using a different production node.

Thus, Intel could deliver nominally 10nm CPUs, which will have various 14nm and 22nm chiplet modules within them (as shown in the graphic below).

And we have a new microarchitecture codename to take note, the “Sunny Cove.” Sunny Cove will be at the heart of Intel’s next-generation Core and Xeon processors in the second half of 2019.

Intel makes some general promises about improving latency and allowing more operations to be executed in parallel (thus acting more like a GPU).

Speaking about GPUs, Intel’s also got new Gen11 integrated graphics “designed to break the 1 TFLOPS barrier,” which will be part of 2019 “10nm-based” processors.