The industry leading chip currently is 10 nanometer (nm) – but researchers in IBM-led Research Alliance, along with their partners including Samsung, have developed an industry-first process to build silicon nanosheet transistors that will enable 5 nanometer (nm) chips.

It was only two years ago that 7nm test node chip was achieved, with 20 billion transistors – now, scientists are ready to start realising 30 billion switches on a fingernail-sized chip. In the words of IBM, “5nm chips are possible, more powerful, and not too far off in the future.”

“Compared to the leading edge 10nm technology available in the market, a nanosheet-based 5nm technology can deliver 40 percent performance enhancement at fixed power, or 75 percent power savings at matched performance. This improvement enables a significant boost to meeting the future demands of artificial intelligence (AI) systems, virtual reality and mobile devices.”

This will allow for improving performance for cognitive computing, the Internet of Things (IoT), and other data-intensive applications delivered in the cloud. With less battery use, batteries in smartphones and other mobile products could last two to three times longer in a single charge.

Up to 7nm node, scientist has been able to rely on the FinFET architecture. However with the 5nm, instead of using FinFET, scientists uses stacks of silicon nanosheets as the device structure of the transistor instead. With current efforts of commercialising 7nm making headway, researchers were are not stopping – pushing for the next generation, bringing 5nm chips into reality, enabling customers “to produce a smaller, faster, and more cost efficient generation of semiconductors.”